The present invention relates to three-dimensional (3D) device packaging fabrication, and more specifically, to wafer to wafer bonding.
Three-dimensional (3D) integrated circuits are chips with two or more layers of active electronic components integrated both vertically and horizontally. This stacking of components (wafers) can reduce cycle time, increase frequency and chip performance, allow more active components to be placed per unit volume, and require fewer pins to communicate among the layers, thereby simplifying the packaging. However, successful 3D integration depends on the strength of the bond between the wafers, because subsequent grinding and chemical mechanical planarization (CMP) steps put stress on the bonds.
Existing wafer bonding techniques apply pressure on the top or bottom or both wafers to press them together. One previous technique involves the application of pressure at the center of the top wafer, pushing it down onto the bottom wafer. Another involves applying pressure at the center of both the top and bottom wafers. Yet another involves applying uniform pressure (several pressure points along the surface) to the top and bottom. However, these techniques leave voids (trapped air) between the wafers that represent areas of incomplete bonding. This incomplete bonding increases the vulnerability of the 3D IC to high mechanical stresses.